1. Field of the Disclosure
Generally, the subject matter disclosed herein relates to the field of integrated circuits, and, more particularly, to the formation of transistors having strained channel regions caused by stressed overlayers, wherein material of spacer elements is partially removed to enhance performance of highly scaled field effect transistors.
2. Description of the Related Art
Modern integrated circuits include a large number of circuit elements, which are formed in a complex manufacturing sequence that may include several hundred process steps, each of which is to be performed under well-controlled conditions in order to meet the required device specification. On the other hand, successful marketing of the semiconductor devices crucially depends on the overall production costs, which are determined by throughput and yield of the overall manufacturing flow. Thus, avoiding one or more of the many complex process steps without negatively affecting the final device performance or enhancing the device performance without significantly contributing additional complexity to the overall process flow are important criteria for semiconductor manufacturers.
Currently, a plurality of process technologies are practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with a weakly or inversely doped channel region disposed between the drain region and the source region.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region is one important factor that determines performance of MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity per unit width, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits, while also allowing an increased packing density, thereby providing the potential for realizing enhanced device functionality for a given available chip area.
The reduction of the transistor dimensions, however, entails a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. One major problem in this respect is the development of enhanced photolithography and etch strategies to reliably and reproducibly create circuit elements of critical dimensions, such as the gate electrode of the transistors, for every new device generation. Moreover, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the drain and source regions to provide low sheet and contact resistivity in combination with a desired channel controllability. In addition, the vertical location of the PN junctions with respect to the gate insulation layer also represents a critical design criterion in view of leakage current control. Hence, reducing the channel length also requires reducing the depth of a portion of the drain and source regions, so-called drain/source extension regions, with respect to the interface formed by the gate insulation layer and the channel region, thereby requiring sophisticated implantation techniques. For this reason, sophisticated spacer techniques are necessary to create the highly complex dopant profile and to serve as a mask in forming metal silicide regions in the gate electrode and the drain and source regions in a self-aligned fashion.
Since the continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation and possibly the new development of process techniques concerning the above-identified process steps, it has been proposed to enhance device performance of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length. One efficient approach in this respect is the modification of the lattice structure in the channel region, for instance by creating tensile or compressive strain, which results in a modified mobility for electrons and holes. For example, creating tensile strain in the channel region formed in a silicon region having a standard crystallographic orientation, i.e., the surface is a (100) equivalent plane and the channel length is oriented along a <110> equivalent axis, increases the mobility of electrons, which in turn directly translates into a corresponding increase in the conductivity and thus transistor performance. On the other hand, compressive stress in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. Consequently, it has been proposed to introduce, for instance, a silicon/germanium layer or a silicon/carbon layer in or below the channel region to create tensile or compressive stress. Although the transistor performance may be considerably enhanced by the introduction of stress-creating layers in or below the channel region, significant efforts have to be made to implement the sequence for forming corresponding stress layers into the conventional and well-approved CMOS technique. For instance, additional epitaxial growth techniques have to be developed and implemented into the process flow to form the germanium- or carbon-containing stress layers at appropriate locations in or below the channel region. Hence, process complexity is significantly increased, thereby also increasing production costs and the potential for a reduction in production yield.
Another promising approach is the creation of stress in the dielectric material, which is formed after finishing the transistor elements to embed and “passivate” the transistors and which receives metal contacts to provide the electrical connection to the drain/source regions and the gate electrode of the transistors. Typically, this dielectric material comprises at least one etch stop layer and a further dielectric layer that may be selectively etched with respect to the etch stop layer. In order to obtain an efficient stress transfer mechanism to the channel region of the transistor for creating strain therein, the contact etch stop layer, that is located in the vicinity of the channel region, has to be positioned closely to the channel region. However, due to the complex dopant profiles that are usually required in highly advanced transistors, an advanced spacer structure is typically provided including three or more individual spacer elements used as implantation masks in respective implantation steps for appropriately positioning the dopants in the drain and source regions on the basis of suitable implantation parameters. A technique using three individual spacer elements for defining the dopant profile in the drain and source regions will hereinafter also be referred to as a triple spacer approach.
In highly scaled transistor architectures, the performance gain obtained by strain-inducing sources and the reduction of the overall transistor dimensions may, however, be less than desirable, due to several problems associated with further device scaling, as will be described with reference to FIGS. 1a-1b in more detail.
FIG. 1a schematically illustrates a semiconductor device 100 comprising a first transistor 150A and a second transistor 150B, which may represent transistors of different conductivity type, or any other neighboring transistors defining a distance 150D therebetween that may be approximately a few hundred nanometers and significantly less, such as 100 nm and less, for highly scaled semiconductor devices. The transistors 150A, 150B are formed above a substrate 101, such as a bulk silicon substrate or a silicon-on-insulator (SOI) substrate, depending on the overall device configuration. Furthermore, a silicon-based semiconductor layer 102 is formed above the substrate 101 and may comprise isolation structures (not shown) used to define active regions, i.e., regions receiving appropriate dopant concentrations for patterning the conductivity of the base silicon material in a required manner. As shown, the silicon-based layer 102 may comprise drain and source regions 151A, 151B having a complex lateral and vertical concentration profile in order to enhance controllability of a corresponding channel region 152, maintain a low overall series resistance, reduce leakage currents and the like. Depending on the conductivity type of the transistors 150A, 150B, the drain and source regions 151A, 151B may be formed on the basis of P-type dopants and N-type dopants, respectively. The transistors 150A, 150B further comprise a gate electrode 153, which, in the manufacturing stage shown, is typically comprised of polysilicon, and which is formed on a gate insulation layer 154 isolating the gate electrode 153 from a channel region 152. The gate insulation layer 154 may be formed on the basis of silicon dioxide, silicon nitride, silicon oxynitride and the like, wherein a thickness of the gate insulation layer 154 for silicon dioxide based materials has reached 2 nm and less, which is near the physical boundaries for the thickness of gate dielectrics based on silicon dioxide with respect to static leakage currents. Hence, other mechanisms may be required for enhanced channel control, such as increasing the charge carry mobility in the channel region 152, unless appropriate dielectric materials having a moderately high permittivity prove to be reliable candidates for replacing silicon dioxide based materials. The gate electrodes 153 have formed on sidewalls thereof a spacer structure 155 that is provided in the example shown as a triple spacer structure comprising an offset spacer 155A comprised of silicon dioxide, a first spacer element 155B and a second spacer element 155C, which are typically made of silicon nitride. Furthermore, the spacer structure 155 comprises a liner material, such as a silicon dioxide liner 155F, separating the first and second spacer elements 155B, 155C. Similarly, a liner 155E may be formed between the offset spacer 155A and the first spacer 155B.
The semiconductor device 100 may be formed on the basis of well-established process techniques, including the definition of isolation structures (not shown), followed by appropriate implantation techniques for defining a desired vertical dopant distribution within and below the channel regions 152. Thereafter, the gate insulation layer 154, in combination with the gate electrode 153, may be formed on the basis of sophisticated oxidation and/or deposition processes, when a silicon dioxide based material is considered for the layer 154, followed by the deposition of an appropriate gate electrode material, such as polysilicon. Next, the gate electrode material and the gate insulation layer may be patterned on the basis of advanced lithography and etch processes, so that a length of the gate electrode 153 may be obtained in the range of 50 nm and less, wherein the distance between neighboring gate electrodes 153 may also be adjusted to approximately 200 nm and even less in densely packed device areas, as previously explained. Next, a portion of the spacer structure 155, i.e., the offset spacer 155A, may be formed with an appropriate spacer width so as to act, in combination with the gate electrode 153, as an implantation mask for defining a portion of the drain and source regions 151A, 151B. The offset spacer 155A may be formed by depositing a silicon dioxide material in a highly conformal manner and subsequently performing a selective plasma-based etch process using well-established etch chemistries, wherein the etch process parameters are adjusted to obtain a high degree of anisotropy. Thereafter, respective implantation processes may be performed, for instance for amorphizing the silicon-based layer 102 down to a specified depth, incorporating the specific type of dopant species for defining a shallow portion of the drain and source regions 151A, 151B and for increasing the concentration of dopants of opposite conductivity type with respect to the drain and source regions 151A, 151B in order to make the corresponding dopant gradients steeper for defining moderately sharp PN junctions. Next, the liner material 155E may be formed by depositing a silicon dioxide layer followed by the deposition of a silicon nitride material with a specified thickness, followed by a highly anisotropic etch process using an etch chemistry that has a high etch selectivity between the liner material and the spacer material. After the anisotropic etch process, the first spacer elements 155B are obtained and may then be used as an efficient implantation mask for performing another implantation process for incorporating dopant species with appropriately selected implantation parameters, such as energy and dose, in order to obtain the desired penetration depth and concentration. Thereafter, the sequence may be repeated to obtain the second spacer elements 155C to establish the final dopant concentration of the drain and source regions 151A, 151B. Intermittently, or after the entire implantation process is completed, appropriate anneal processes may be performed to re-crystallize the material in the drain and source regions 151A, 151B and to activate the implanted dopant atoms. As previously explained, by using the triple spacer structure 155, the drain and source regions 151A, 151B may be shaped in the vertical and lateral directions so as to obtain a desired high performance of the transistors 150A, 150B. On the other hand, defining the dopant profile of the drain and source regions 151A, 151B on the basis of a less complex spacer structure, for instance by omitting the first spacer element 155B and thus the associated implantation process, in view of enhanced overall process efficiency, may result in reduced performance, since a reduced conductivity of the N-channel transistors may be observed while also increased implantation dose values may have to used for the P-channel transistors to obtain the desired depth of the drain and source regions. That is, for N-channel transistors, the second implantation process may be specifically designed for reducing the series resistance of the drain and source regions, which may be difficult to be achieved on the basis of a single implantation process using the spacer structure in its final state. Similarly, for P-channel transistors, the adjustment of the desired depth of the drain and source regions may be difficult in a single deep drain/source implantation process, in particular when an SOI configuration is considered, in which the P-type dopant is to be placed such that it connects to the buried insulating layer. Hence, when balancing advantages with respect to less complex process flow of a double spacer approach, i.e., offset spacer plus single outer spacer, against the performance gain obtained by the triple spacer approach described above, usually the triple spacer approach is favored.
As previously discussed, additional performance gain may be obtained by inducing a certain type of strain in the channel regions 152, for instance by providing a highly stressed material above the transistors 150A, 150B, wherein the magnitude of strain may depend on the amount and intrinsic stress level of the respective material.
FIG. 1b schematically illustrates the semiconductor device 100 with a first stressed dielectric layer 103A, which may represent a contact etch stop layer, above the first transistor 150A, while a second contact etch stop layer 103AB with a high intrinsic stress level may be formed above the second transistor 150B. In the example shown, the layer 103A has a high compressive stress to induce a respective compressive strain in the channel region 152 of the transistor 150A. Similarly, the transistor 150B may receive a tensile strain caused by a high intrinsic tensile stress of the layer 103AB. Moreover, the transistors 150A, 150B comprise metal silicide regions 105 formed on the drain and source regions 151A, 151B and metal silicide regions 104 formed on the gate electrode 153. Typically, the metal silicide regions 104, 105 may be formed in a common process sequence, for instance on the basis of cobalt, nickel and the like, by depositing a metal layer and initiating a chemical reaction during which the spacer structure 155 exhibits a substantially inert behavior so that non-reacted metal may be readily removed from the spacer structure 155, thereby substantially avoiding the creation of undesired conductive paths between the metal silicide regions 104 and 105. Thereafter, the etch stop layers 103A, 103AB may be formed on the basis of well established deposition and patterning regimes, for instance using silicon nitride material, which may be efficiently deposited by plasma enhanced chemical vapor deposition (PECVD) with a desired high intrinsic stress level. Thereafter, an interlayer dielectric material may be deposited, such as silicon dioxide, which may then be patterned to receive respective contact openings, which may extend down to the metal silicide regions 105.
Thus, for reduced distances 150D (see FIG. 1a), the amount of stressed material of the layers 103A, 103AB may be restricted due to the limitations of the gap fill capabilities of the respective patterning sequence for forming the stress layers 103A, 103AB. Moreover, the stress transfer mechanism provided by the layers 103A, 103AB may be reduced by the subsequent formation of contact openings, since the respective openings may remove a significant portion of the stressed dielectric material in densely packed device areas. Thus, for highly scaled semiconductor devices, the efficiency of the stress transfer mechanism may be significantly reduced. Furthermore, as previously explained, an important factor for the overall transistor performance is the gate series resistance, which strongly depends on the conductivity and the thickness of the metal silicide region 104. Thus, for a reduced channel length, the overall amount of metal silicide in the region 104 may also be reduced, thereby increasing the series resistance of the gate electrode 153, which may translate into increased switching times and thus reduced transistor performance for sophisticated logic devices.
In view of this situation, it has been proposed to remove the outer spacer of the spacer structure 155 prior to performing the silicidation process, thereby at least increasing the amount of metal silicide in the regions 105 and also providing the possibility of positioning an increased amount of highly stressed material in the vicinity of the channel regions 152 so that the formation of the contact openings may have a less pronounced effect on the overall stress transfer mechanism. This approach may result in enhanced transistor performance, thereby, however, requiring additional process steps, which may increase overall production costs.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.